38 lines
670 B
Text
38 lines
670 B
Text
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`timescale 1ns / 1ps
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/**
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* counter: a generic clearable up-counter
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*/
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module counter
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#(parameter WIDTH=64)
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(
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input clk,
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input ce,
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input arst_n,
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output reg [WIDTH-1:0] q
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);
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// some child
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clock_buffer #(WIDTH) buffer_inst (
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.clk(clk),
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.ce(ce),
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.reset(arst_n)
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);
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// Simple gated up-counter with async clear
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always @(posedge clk or negedge arst_n) begin
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if (arst_n == 1'b0) begin
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q <= {WIDTH {1'b0}};
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end
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else begin
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q <= q;
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if (ce == 1'b1) begin
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q <= q + 1;
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end
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end
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end
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endmodule
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