42 lines
1 KiB
Text
42 lines
1 KiB
Text
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/*
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* RS-trigger with assynch. reset
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*/
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library ieee;
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use ieee.std_logic_1164.all;
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entity RS_trigger is
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generic (T: Time := 0ns);
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port ( R, S : in std_logic;
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Q, nQ : out std_logic;
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reset, clock : in std_logic );
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end RS_trigger;
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architecture behaviour of RS_trigger is
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signal QT: std_logic; -- Q(t)
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begin
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process(clock, reset) is
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subtype RS is std_logic_vector (1 downto 0);
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begin
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if reset = '0' then
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QT <= '0';
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else
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if rising_edge(C) then
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if not (R'stable(T) and S'stable(T)) then
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QT <= 'X';
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else
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case RS'(R&S) is
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when "01" => QT <= '1';
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when "10" => QT <= '0';
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when "11" => QT <= 'X';
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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Q <= QT;
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nQ <= not QT;
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end architecture behaviour;
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